教育、科研工作经历 2005 - 2009 清华大学 电子科学与技术专业 工学学士 2009 - 2015 清华大学 电子科学与技术专业 工学博士 2015 - 2017 北京理工大学 信息与电子学院 博士后 2017 至今 上海大学 通信与信息工程学院 讲师、副教授 研究方向 ● 数字大规模集成电路设计、片上系统 (SoC) 设计 ● 领域定制处理器架构、并行计算 ● 数字无线通信系统、基带处理器、无线信道编译码器设计 ● 深度学习、神经网络加速芯片、模型压缩与网络模型轻量化 获奖、荣誉与学术兼职
● 2017年上海市海外高层次人才计划 ● 2020年上海大学蔡冠深优秀青年教师 ● IEEE circuits and systems society COMCAS technical committee member ● IEEE ISCAS review committee member ● ICTC 2022 special session chair, IEEE SiPS 2019 special session chair. etc. 科研项目
（1） 校企合作项目，面向6G低空网络的通信芯片，2024-2025，主持。 （2） 校企合作项目，数字波束合成及测向算法，2024，主持。 （3） 校企合作项目，高性能ADC芯片DDC模块开发，2022-2023，主持。 （4） 校企合作项目，面向智能无人车的C-V2X FPGA系统模组设计，2022-2023，参与。 （5） 上海市自然科学基金面上项目，面向下一代无线通信的信道译码异构融合机制研究，2021-2024，主持。 （6） 国家自然科学基金青年项目，基于深度学习的通用信道译码异构架构研究， 2020-2022 ，主持。 （7） 国家重点实验室开放课题，基于时间敏感网络的机器人高确定性信息交互技术研究，2019-2020 ，主持。 （8） 国家重点研发计划政府间国际科技创新合作重点专项， 支撑未来自动驾驶的网络研究，2019-2020，参与。 （9） 国家重大专项，基于 R15 5G 终端试验样机研发，2018-2019，参与。 教学经历
● 并行与分布式计算 (Fall 2022-2024) ● 面向复杂对象的可测性设计与故障容错设计 (Spring 2020~2024) ● 通信电子线路 (Spring 2019~2024) ● 数字电路 (Fall 2016~2017) 近五年代表性成果
[1] S. Cao, S. Chen, L. Jiang and Z. Jiang, "A Critical-Set-Based Multi-Bit Successive Cancellation List Decoder for Polar Codes: Algorithm and Implementation," in IEEE Transactions on Circuits and Systems I: Regular Papers, early access. [2] Y. Li, S. Cao, B. Zhao, W. Zhang and Z. Jiang, "Hybrid-Grained Pruning and Hardware Acceleration for Convolutional Neural Networks," 2024 IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, Singapore, 2024, pp. 1-5. [3] B. Ruan, L. Jiang, S. Cao and Z. Jiang, "Dynamically Configurable FIR Filters Based on Serial MACs and Systolic Arrays," 2024 IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, Singapore, 2024, pp. 1-5. [4] F. Ye, F. Yuan, S. Cao, Z. Jiang and S. Zhou, "SPMD-Based Mixed-Radix FFT and Channel Estimation for Energy-Efficient O-RAN," 2023 International Conference on Future Communications and Networks (FCN), Queenstown, New Zealand, 2023, pp. 1-6. [5] Y. Shen, F. Yuan, S. Cao, Z. Jiang and S. Zhou, "Parallel Computing for Energy-Efficient Baseband Processing in O-RAN: Synchronization and OFDM Implementation Based on SPMD," GLOBECOM 2023 - 2023 IEEE Global Communications Conference, Kuala Lumpur, Malaysia, 2023, pp. 2736-2741. [6] M. Yang, S. Cao, W. Zhang, Y. Li and Z. Jiang, "Loop-Tiling Based Compiling Optimization for CNN Accelerators," 2023 IEEE 15th International Conference on ASIC (ASICON), Nanjing, China, 2023. [7] W. Zhang et al., "An FPGA-based Low Latency Sensing and Communication Platform for Collaborative Autonomous Driving," 2023 IEEE 24th International Workshop on Signal Processing Advances in Wireless Communications (SPAWC), Shanghai, China, 2023. [8] S. Cao, H. Hu, L. Jiang, etc, "A Domain Specific Computing Architecture for Open 6G Baseband Signal Processing," ACM Turing Award Celebration Conference - China 2023 (ACM TURC '23). Association for Computing Machinery, New York, NY, USA, 21–22. [9] R. Jiang, Z. Fei, S. Cao, etc. "Deep learning-aided signal detection for two-stage index modulated universal filtered multi-carrier systems," IEEE Transactions on Cognitive Communications and Networking, 8(1), 136–154. [10] Q. Sun, S. Cao, and Z. Chen, "Filter Pruning via Automatic Pruning Rate Search", Proceedings of the Asian Conference on Computer Vision (ACCV), 2022, pp. 4293-4309. [11] L. Hui, S. Cao, Z. Chen, S. Li and S. Xu, "Configurable CNN Accelerator in Speech Processing based on Vector Convolution," 2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS), Incheon, Korea, Republic of, 2022, pp. 146-149. [12] C. Zhang, H. Hu, S. Cao and Z. Jiang, "A Novel Blind Detection Method and FPGA Implementation for Energy-Efficient Sidelink Communications," 2021 IEEE Workshop on Signal Processing Systems (SiPS), Coimbra, Portugal, 2021, pp. 7-11. [13] A. Nahli, S. Cao, Z. Jia, R. Ma and S. Xu, "Dataset and Network Structure: Towards Frames Selection for Fast Video Deblurring," in IEEE Access, vol. 9, pp. 61369-61382, 2021. [14] H. Wang, S. Cao and S. Xu, "A Real-Time Face Recognition System by Efficient Hardware-Software Co-Design on FPGA SoCs," 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS), Washington DC, DC, USA, 2021. [15] S. Cao, L. Jiang, T. Lin, S. Zhang and S. Xu, "A Semi-Folded Decoding Architecture for Flexible Codeword Length Configuration of Polar Codes," 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea, 2021, pp. 1-5. [16] S. Cao, T. Lin, S. Zhang, S. Xu and C. Zhang, "A Reconfigurable and Pipelined Architecture for Standard-Compatible LDPC and Polar Decoding," in IEEE Transactions on Vehicular Technology, vol. 70, no. 6, pp. 5431-5444, June 2021. [17] S. Cao, W. Deng, Z. Bao, C. Xue, S. Xu and S. Zhang, "SimuNN: A Pre-RTL Inference, Simulation and Evaluation Framework for Neural Networks," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 10, no. 2, pp. 217-230, June 2020. [18] S. Cao, H. Zheng, T. Lin, S. Zhang and S. Xu, "An Unfolded Pipelined Polar Decoder With Hybrid Number Representations for Multi-User MIMO Systems," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 11, pp. 2472-2476, Nov. 2020. [19] Z. Jiang, Z. Cao, S. Fu, F. Peng, S. Cao, etc, "Revealing much while saying less: Predictive wireless for status update," IEEE infocom 2020 - IEEE conference on computer communications, 2020, pp. 1419–1428. [20] H. Wang, S. Cao, S. Xu, etc, "Hardware-software co-design for face recognition on FPGA SoCs," 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, pp. 1–5. |